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| A29DL324 Series 32M-Bit CMOS Low Voltage Dual Operation Flash Memory Preliminary 4M-Byte by 8-Bit (Byte Mode) / 2M-Word by 16-Bit (Word Mode) Features n Two bank organization enabling simultaneous execution of erase / program and read n Bank organization: 2 banks (16 Mbits + 16 Mbits) n Memory organization: - 4,194,304 words x 8 bits (BYTE mode) - 2,097,152 words x 16 bits (WORD mode) n Sector organization: 71 sectors (8 Kbytes / 4 Kwords x 8 sectors, 64 Kbytes / 32 Kwords x 63 sectors) n 2 types of sector organization - T type: Boot sector allocated to the highest address (sector) - B type: Boot sector allocated to the lowest address (sector) n 3-state output n Automatic program - Program suspend / resume n Unlock bypass program n Automatic erase - Chip erase - Sector erase (sectors can be combined freely) n Erase suspend / resume n Program / Erase completion detection - Detection through data polling and toggle bits - Detection through RY/ BY pin n Sector group protection - Any sector group can be protected - Any protected sector group can be temporary unprotected n Sectors can be used for boot application n Hardware reset and standby using RESET pin n Automatic sleep mode n Boot block sector protect by WP (ACC) pin n Conforms to common flash memory interface (CFI) n Extra One Time Protect Sector provided Part No. Access time (Max.) Operating Power supply current Standby supply (Active mode) current voltage (Max.) (Max.) A29DL324 90ns 2.7V~ 3.6V 16mA 30mA 5A n Operating ambient temperature: -40 to 85C n Program / erase time - Program: 9.0 s / byte (TYP.) 11.0 s / word (TYP.) - Sector erase: 0.7 s (TYP.) n Number of program / erase: 1,000,000 times (MIN.) n Package options - 48-pin TSOP (I) or 63-ball TFBGA General Description The A29DL324 is a flash memory organized of 33,554,432 bits and 71 sectors. Sectors of this memory can be erased at a low voltage (2.7 to 3.6 V) supplied from a single power source, or the contents of the entire chip can be erased. Two modes of memory organization, BYTE mode (4,194,304 words x 8 bits) and WORD mode (2,097,152 words x 16 bits), are selectable so that the memory can be programmed in byte or word units. The A29DL324 can be read while its contents are being erased or programmed. The memory cell is divided into two banks. While sectors in one bank are being erased or programmed, data can be read from the other bank thanks to the simultaneous execution architecture. The banks are 8 Mbits and 24 Mbits. This flash memory comes in two types. The T type has a boot sector located at the highest address (sector) and the B type has a boot sector at the lowest address (sector). Because the A29DL324 enables the boot sector to be erased, it is ideal for storing a boot program. In addition, program code that controls the flash memory can be also stored, and the program code can be programmed or erased without the need to load it into RAM. Eight small sectors for storing parameters are provided, each of which can be erased in 8 Kbytes units. Once a program or erase command sequence has been executed, an automatic program or automatic erase function internally executes program or erase and verification automatically. Because the A29DL324 can be electrically erased or programmed by writing an instruction, data can be reprogrammed on-board after the flash memory has been installed in a system, making it suitable for a wide range of applications. PRELIMINARY (May, 2002, Version 0.0) 1 AMIC Technology, Inc. A29DL324 Series Pin Configurations n TSOP (I) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET NC WP (ACC) RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND I/O 15 (A-1) I/O 7 I/O 14 I/O 6 I/O 13 I/O 5 I/O 12 I/O 4 VCC I/O 11 I/O 3 I/O 10 I/O 2 I/O 9 I/O 1 I/O 8 I/O 0 OE GND CE A0 A29DL324V n TFBGA Top View Bottom View 8 7 6 5 4 3 2 1 ABCDEFGHJKLM MLKJHGFEDCBA A 1 2 3 4 5 6 7 8 NC NC NC NC B NC NC C A13 A9 D A12 A8 E A14 A10 NC A18 A6 A2 Top View F A15 A11 A19 A20 A5 A1 G A16 I/O7 I/O5 I/O2 I/O0 A0 H J K L NC NC M NC NC WE RESET BYTE I/O15(A-1) GND I/O14 I/O13 I/O6 I/O12 VCC I/O4 I/O10 I/O8 I/O11 I/O9 I/O3 I/O1 GND RY/BY WP (ACC) A7 A17 A3 A4 NC CE OE NC NC NC NC PRELIMINARY (May, 2002, Version 0.0) 2 AMIC Technology, Inc. A29DL324 Series Block Diagram VCC GND Address Buffers Bank 2 Address Address Latch X-Decoder Cell Matrix (Bank 2) A0-A20 Y-Decoder Y-Gating Bank / Sector Decoder WP(ACC) Program / Erase Voltage Generator RESET WE BYTE CE OE State Control (Command Register) SA / WC I/O0 - I/O 15 (A-1) Data Latch Input / Output Buffers SA / WC RY/BY Address Latch Y-Decoder Y-Gating Bank 1 Address X-Decoder Cell Matrix (Bank 1) Pin Descriptions Pin No. A0 - A20 I/O0 - I/O14 I/O15 I/O15 (A-1) A-1 Description Address Inputs Data Inputs/Outputs Data Input/Output, Word Mode LSB Address Input, Byte Mode Chip Enable Write Enable Output Enable Hardware Reset Input Mode Select Ready/ BUSY - Output Write Protect (Accelerated) Input Ground Power Supply No Connection CE WE OE RESET BYTE RY/BY WP (ACC) GND VCC NC Note Note: Some signals can be applied because this pin is not connected to the inside of the chip. PRELIMINARY (May, 2002, Version 0.0) 3 AMIC Technology, Inc. A29DL324 Series Input / Output Pin Function Pin Name A0 to A20 Input / Output Input Function Address input pins. A0 to A20 are used differently in the BYTE mode and the WORD mode. BYTE MODE A0 to A20 are used as the upper 21 bits of total 22 bits of address input pin. (The least significant bit (A-1) is combined to I/O15.) WORD MODE A0 to A20 are used as 21 bits address input pin. Data input / output pins. I/O0 to I/O14 are used differently in the BYTE mode and the WORD mode. BYTE MODE I/O0 to I/O7 are used as the 8 bits data input / output pins. I/O8 to I/O14 are Hi-Z. WORD MODE I/O0 to I/O14 are used as the lower 15 bits of total 16 bits of data input / output pins. (The most significant bit (I/O15) is combined to A-1.) I/O15, A1 are used differently in the BYTE mode and the WORD mode. BYTE MODE The least significant address input pin (A-1) WORD MODE The most significant data input / output pin (I/O15) This pin inputs the signal that activates the chip. When high level, the chip enters the standby mode. This pin inputs the read operation control signal. When high level, output is Hi-Z. This pin inputs the write operation control signal. When low level, command input is accepted. The pin for switching BYTE mode and WORD mode. High level : WORD MODE (2M words x 16 bits) Low level : BYTE MODE (4M words x 8 bits) This pin inputs hardware reset. When low level, hardware reset is performed. If 11.5 to 12.5 V is applied to RESET, the chip enters the temporary sector group unprotect mode. This pin indicates whether automatic program / erase is currently being executed. It uses open drain connection. Low level indicates the busy state during which the device is performing automatic program erase. High level indicates the device is in the ready state and will accept the next operation. In this case, the device is either in the erase suspend mode or the standby mode. This pin selects the boot block sector protect mode or accelerated mode. Low level: The boot block (2 sectors) is protected. High level: The boot block is unprotected. VACC level: Accelerated mode is selected. Supply Voltage Ground No Connection I/O0 to I/O14 Input / Output I/O15, A-1 Input / Output CE OE WE Input Input Input Input BYTE RESET Input RY/BY Output WP (ACC) Input VCC GND NC - PRELIMINARY (May, 2002, Version 0.0) 4 AMIC Technology, Inc. A29DL324 Series Absolute Maximum Ratings* Storage Temperature (Tstg) . . . . . . . . . . -55C to + 125C Operating Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to + 85C Input / Output Voltage with Respect to GND WP (ACC), RESET . . . . . . . . . . . . -0.5V Note1 to 13.0V All Pins except WP (ACC), RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V Note1 to VCC + 0.4 (4.0V max.) Note2 Supply Voltage with Respect to GND (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Operating Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) . . . . . . . . . . . . . . . . . +2.7V to +3.6V Notes: 1. 2. -2.0V (Min.) (Pulse width 20ns) VCC + 0.5V (Max.) (Pulse width 20ns) Bus Operations The following table shows the operation modes of the dual operation flash memory. Before turning on power, input GND 0.2 V to the RESET until VCC VCC (min.). Table 1. A29DL324 Bus Operations Operation Read (Note) Write BYTE mode WORD mode BYTE mode WORD mode CE L L L L H X L X L L X L L OE L L H H X X H X L L X H H WE H H L L X X H X H H X L L I/O15, A-1 A-1 X A-1 X X X X X A-1 X X A-1 X A6 A1 A0 Standby Hardware reset / Standby Output Disable Temporary Sector Group Unprotect Automatic Sleep Mode BYTE mode WORD mode Boot Block Sector Protect Accelerated Mode BYTE mode WORD mode Address input Address input Address input Address input X X X X X X X X X X X X Address input Address input X X X Address input Address input I/O8 to RESET WP I/O15 (ACC) Data output Hi-Z H X Data output H X Data input Hi-Z H Note3 Data input H Note3 Hi-Z Hi-Z H X Hi-Z Hi-Z L X Hi-Z Hi-Z H X Hi-Z or VID Note3 Data input / output Data output Hi-Z H X Data output H X Hi-Z or X L Data input / output Data input Hi-Z H VACC Data input H VACC I/O0 to I/O7 Note: When OE = VIL, VIL can be applied to WE . When OE = VIH, a write operation is started. Remarks: 1. H : VIH, L : VIL, : VIH or VIL, VID : 11.5 V to 12.5 V, VACC : 8.5 V to 9.5 V 2. If an address is held longer than the minimum read cycle time (tRC), the automatic sleep mode is set. 3. If WP (ACC)=VIL, sector 0,1,140, and 141 remain protected. If WP (ACC)=VIH, protection on sectors 0,1,140, and 141 depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP (ACC)=VHH, all sectors will be unprotected. PRELIMINARY (May, 2002, Version 0.0) 5 AMIC Technology, Inc. A29DL324 Series Read Operation The read operation is controlled by the OE and /OE. The /CE is used to select a device, and the OE controls data output. The following three access times are used depending on the condition. - Address access time (tACC): Time until valid data is output after an address has been determined (however, after CE ). - Hardware Reset Pin The device is reset to the read mode if VIL is input to the RESET for the duration of tRP and VIH for the duration of tRH. While VIL is being input to the RESET , all commands are ignored, and the output pins go into a Hi-Z state. If the voltage on RESET is kept to GND 0.2 V at this time, the current consumption can be lowered to 5A or less. If VIH is input to the RESET , tREADY is required until data is output. For the timing waveform, refer to Timing Waveform for Read Cycle (2). CE access time (tCE): Time until valid data is output after CE has been determined (however, after address). OE access time (tOE): Time until valid data is output Output Disable Mode Output from the device is disabled (Hi-Z state) if VIH is input to the OE . - after OE has been determined (however, OE must be input after tACC-tOE, tCE-tOE after address and CE have been determined). On power-up, the device is automatically set in the read mode. To read the device without changing address immediately after power application, either execute hardware reset or briefly lower CE to VIL from VIH. For the timing waveform, refer to Timing Waveform for Read Cycle (1). Sector Group Protection Protect the sector group by using a command. OE or WE control is no need. Temporary Sector Group Unprotect Protection of a sector group can be temporarily canceled. When VID is input to RESET , the temporary sector group unprotect mode is set. If a protected sector is selected in this mode, it can be programmed or erased. If the mode is canceled, the sector group is protected again. For the timing waveform, refer to Timing Waveform for Temporary Sector Group Unprotect. Write Operation The operation of the device is controlled by writing commands to the registers. The command register is a function that latches the address and data necessary for executing an instruction and does not occupy the memory area. If an illegal address or data is written or if an address or data is written in the wrong sequence, the device is reset to the read mode. Product ID Read the product ID code by using a command. Standby Mode The standby mode is set when VIH is input to the CE . The current consumption in the standby mode can be lowered to 5 A or less in two ways. One is to use CE and RESET . Input VCC 0.3 V to CE and RESET . However, while automatic programming or erasing is being executed, the operating supply current (ICC2) does not decrease to 5A or lower even if CE = VIH. If a read operation is executed in the standby mode, data is output at CE access time. The other is to input GND 0.3 V to the RESET . At this time, the level of CE is VIH or VIL. In this case, tRH is required for the device to return to the read mode from the standby mode. For the timing waveform, refer to Timing Waveform for Read Cycle (2). Automatic Sleep Mode The automatic sleep mode is used to reduce the power consumption substantially during a read operation. If an address is held longer than the minimum read cycle time (tRC), the sleep mode (low power consumption mode) is automatically set. In this mode, the output data is latched and continuously output. In the automatic sleep mode, CE , WE , and OE do not have to be controlled. At this time, the current consumption decreases to 5A or less. During dual operation, however, the current consumption is power supply current (ICC6, ICC7). If the address is changed, the automatic sleep mode is canceled automatically, the device returns to the read mode, and the data of the newly input address is output. PRELIMINARY (May, 2002, Version 0.0) 6 AMIC Technology, Inc. A29DL324 Series Boot Block Sector Protect The boot block sector protect mode protects the two sectors of the boot block. This mode is set when VIL is input to WP (ACC). If VIL is input to WP (ACC) even in the temporary sector group unprotect mode, the boot block remains protected and protection of the other sectors is temporarily canceled. In the accelerated mode, protection of the sector group is temporarily canceled. Exercise care in programming the device at this time. For the timing waveform, refer to Timing Waveform for Accelerated Mode. Dual Operation This device can execute a program or erase operation and a read operation simultaneously. By selecting bank 1 or 2 by changing the bank address, one bank can execute a read operation while the other bank is executing a program or erase operation. When changing the bank address, no wait cycle is necessary. Note that two or more program or erase operation. When changing the bank address, no wait cycle is necessary. Note that two or more operations cannot be executed at the same time in the same bank. The following table shows the combinations of bank operations. For the timing waveform, refer to Timing Waveform for Dual Operation. Accelerated Mode This mode is used to program the device at high speed, and the programming time can be shortened to about 60%. To program the device in the accelerated mode, input VACC to WP (ACC) and use an unlock bypass program command. Therefore, ordinary commands can be used for programming or detection of completion of programming. If VACC is input to WP (ACC), the device is automatically set in the unlock bypass mode. Therefore, the unlock bypass set command and reset command are not necessary. The accelerated mode is automatically canceled if the input of VACC to WP (ACC) is stopped. Table 2. Dual Operation Case 1 2 3 4 5 6 7 Operation of Bank 1 Read mode Read mode Read mode Read mode Product ID Program (Note 1) Erase (Note 2) Operation of Bank 2 Read mode Product ID Program (Note 1) Erase (Note 2) Read mode Read mode Read mode Notes 1. The program operation is suspended by the program suspend command, and addresses not being programmed to at this time can only be read. 2. The erase operation is suspended by the erase suspend command. The sector not erased at this time can be read or programmed. PRELIMINARY (May, 2002, Version 0.0) 7 AMIC Technology, Inc. A29DL324 Series Table 3. A29DL324 Top Boot Block Sector Address Table Bank Sector Sector Address Table Bank Address Table A20 A19 A18 A17 A16 A15 A14 A13 A12 Bank 1 SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 SA36 SA35 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) Byte Mode (x 8) Word Mode (x16) 3FFFFFH-3FE000H 1FFFFFH-1FF000H 3FDFFFH-3FC000H 1FEFFFH-1FE000H 3FBFFFH-3FA000H 1FDFFFH-1FD000H 3F9FFFH-3F8000H 1FCFFFH-1FC000H 3F7FFFH-3F6000H 3F5FFFH-3F4000H 3F3FFFH-3F2000H 3F1FFFH-3F0000H 3EFFFFH-3E0000H 1FBFFFH-1FB000H 1FAFFFH-1FA000H 1F9FFFH-1F9000H 1F8FFFH-1F8000H 1F7FFFH-1F0000H 3DFFFFH-3D0000H 1EFFFFH-1E8000H 3CFFFFH-3C0000H 1E7FFFH-1E0000H 3BFFFFH-3B0000H 1DFFFFH-1D8000H 3AFFFFH-3A0000H 1D7FFFH-1D0000H 39FFFFH-390000H 38FFFFH-380000H 37FFFFH-370000H 36FFFFH-360000H 35FFFFH-350000H 34FFFFH-340000H 33FFFFH-330000H 32FFFFH-320000H 31FFFFH-310000H 30FFFFH-300000H 2FFFFFH-2F0000H 2EFFFFH-2E0000H 2DFFFFH-2D0000H 2CFFFFH-2C0000H 2BFFFFH-2B0000H 2AFFFFH-2A0000H 29FFFFH-290000H 28FFFFH-280000H 27FFFFH-270000H 26FFFFH-260000H 25FFFFH-250000H 24FFFFH-240000H 23FFFFH-230000H 1CFFFFH-1C8000H 1C7FFFH-1C0000H 1BFFFFH-1B8000H 1B7FFFH-1B0000H 1AFFFFH-1A8000H 1A7FFFH-1A0000H 19FFFFH-198000H 197FFFH-190000H 18FFFFH-188000H 187FFFH-180000H 17FFFFH-178000H 177FFFH-170000H 16FFFFH-168000H 167FFFH-160000H 15FFFFH-158000H 157FFFH-150000H 14FFFFH-148000H 147FFFH-140000H 13FFFFH-138000H 137FFFH-130000H 12FFFFH-128000H 127FFFH-120000H 11FFFFH-118000H PRELIMINARY (May, 2002, Version 0.0) 8 AMIC Technology, Inc. A29DL324 Series Table 3. A29DL324 Top Boot Block Sector Address Table (continued) Bank Sector Sector Address Table Bank Address Table A20 A19 A18 A17 A16 A15 A14 A13 A12 Bank 1 SA34 SA33 SA32 Bank 2 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) Byte Mode (x 8) 22FFFFH-220000H 21FFFFH-210000H 20FFFFH-200000H 1FFFFFH-1F0000H 1EFFFFH-1E0000H Word Mode (x16) 117FFFH-110000H 10FFFFH-108000H 107FFFH-100000H 0FFFFFH-0F8000H 0F7FFFH-0F0000H 1DFFFFH-1D0000H 0EFFFFH-0E8000H 1CFFFFH-1C0000H 0E7FFFH-0E0000H 1BFFFFH-1B0000H 0DFFFFH-0D8000H 1AFFFFH-1A0000H 0D7FFFH-0D0000H 19FFFFH-190000H 18FFFFH-180000H 17FFFFH-170000H 16FFFFH-160000H 15FFFFH-150000H 14FFFFH-140000H 13FFFFH-130000H 12FFFFH-120000H 11FFFFH-110000H 10FFFFH-100000H 0FFFFFH-0F0000H 0EFFFFH-0E0000H 0DFFFFH-0D0000H 0CFFFFH-0C0000H 0BFFFFH-0B0000H 0AFFFFH-0A0000H 09FFFFH-090000H 08FFFFH-080000H 07FFFFH-070000H 06FFFFH-060000H 05FFFFH-050000H 04FFFFH-040000H 03FFFFH-030000H 02FFFFH-020000H 01FFFFH-010000H 00FFFFH-000000H 0CFFFFH-0C8000H 0C7FFFH-0C0000H 0BFFFFH-0B8000H 0B7FFFH-0B0000H 0AFFFFH-0A8000H 0A7FFFH-0A0000H 09FFFFH-098000H 097FFFH-090000H 08FFFFH-088000H 087FFFH-080000H 07FFFFH-078000H 077FFFH-070000H 06FFFFH-068000H 067FFFH-060000H 05FFFFH-058000H 057FFFH-050000H 04FFFFH-048000H 047FFFH-040000H 03FFFFH-038000H 037FFFH-030000H 02FFFFH-028000H 027FFFH-020000H 01FFFFH-018000H 017FFFH-010000H 00FFFFH-008000H 007FFFH-000000H PRELIMINARY (May, 2002, Version 0.0) 9 AMIC Technology, Inc. A29DL324 Series Table 4. A29DL324 Bottom Boot Block Sector Address Table Bank Sector Sector Address Table Bank Address Table A20 A19 A18 A17 A16 A15 A14 A13 A12 Bank 2 SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 Bank 1 SA38 SA37 SA36 SA35 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) Byte Mode (x 8) 3FFFFFH-3F0000H 3EFFFFH-3E0000H Word Mode (x16) 1FFFFFH-1F8000H 1F7FFFH-1F0000H 3DFFFFH-3D0000H 1EFFFFH-1E8000H 3CFFFFH-3C0000H 1E7FFFH-1E0000H 3BFFFFH-3B0000H 1DFFFFH-1D8000H 3AFFFFH-3A0000H 1D7FFFH-1D0000H 39FFFFH-390000H 38FFFFH-380000H 37FFFFH-370000H 36FFFFH-360000H 35FFFFH-350000H 34FFFFH-340000H 33FFFFH-330000H 32FFFFH-320000H 31FFFFH-310000H 30FFFFH-300000H 2FFFFFH-2F0000H 2EFFFFH-2E0000H 2DFFFFH-2D0000H 2CFFFFH-2C0000H 2BFFFFH-2B0000H 2AFFFFH-2A0000H 29FFFFH-290000H 28FFFFH-280000H 27FFFFH-270000H 26FFFFH-260000H 25FFFFH-250000H 24FFFFH-240000H 23FFFFH-230000H 22FFFFH-220000H 21FFFFH-210000H 20FFFFH-200000H 1FFFFFH-1F0000H 1EFFFFH-1E0000H 1CFFFFH-1C8000H 1C7FFFH-1C0000H 1BFFFFH-1B8000H 1B7FFFH-1B0000H 1AFFFFH-1A8000H 1A7FFFH-1A0000H 19FFFFH-198000H 197FFFH-190000H 18FFFFH-188000H 187FFFH-180000H 17FFFFH-178000H 177FFFH-170000H 16FFFFH-168000H 167FFFH-160000H 15FFFFH-158000H 157FFFH-150000H 14FFFFH-148000H 147FFFH-140000H 13FFFFH-138000H 137FFFH-130000H 12FFFFH-128000H 127FFFH-120000H 11FFFFH-118000H 117FFFH-110000H 10FFFFH-108000H 107FFFH-100000H 0FFFFFH-0F8000H 0F7FFFH-0F0000H 1DFFFFH-1D0000H 0EFFFFH-0E8000H 1CFFFFH-1C0000H 0E7FFFH-0E0000H PRELIMINARY (May, 2002, Version 0.0) 10 AMIC Technology, Inc. A29DL324 Series Table 4. A29DL324 Bottom Boot Block Sector Address Table (continued) Bank Sector Sector Address Table Bank Address Table A20 A19 A18 A17 A16 A15 A14 A13 A12 Bank 1 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) Byte Mode (x 8) Word Mode (x16) 1BFFFFH-1B0000H 0DFFFFH- 0D8000H 1AFFFFH-1A0000H 0D7FFFH- 0D0000H 19FFFFH-190000H 0CFFFFH-0C8000H 18FFFFH-180000H 0C7FFFH-0C0000H 17FFFFH-170000H 0BFFFFH-0B8000H 16FFFFH-160000H 0B7FFFH-0B0000H 15FFFFH-150000H 0AFFFFH-0A8000H 14FFFFH-140000H 0AFFFFH-0A0000H 13FFFFH-130000H 09FFFFH-098000H 12FFFFH- 120000H 097FFFH- 090000H 11FFFFH-110000H 10FFFFH-100000H 0FFFFFH-0F0000H 0EFFFFH-0E0000H 08FFFFH-088000H 087FFFH-080000H 07FFFFH-078000H 077FFFH-070000H 0DFFFFH-0D0000H 06FFFFH-068000H 0CFFFFH-0C0000H 067FFFH-060000H 0BFFFFH-0B0000H 05FFFFH-058000H 0AFFFFH-0A0000H 09FFFFH-090000H 08FFFFH-080000H 07FFFFH-070000H 06FFFFH-060000H 05FFFFH-050000H 04FFFFH-040000H 03FFFFH-030000H 02FFFFH-020000H 01FFFFH-010000H 00FFFFH-00E000H 00DFFFH-00C000H 00BFFFH-00A000H 009FFFH-008000H 007FFFH-006000H 005FFFH-004000H 003FFFH-002000H 001FFFH-000000H 057FFFH-050000H 04FFFFH-048000H 047FFFH-040000H 03FFFFH-038000H 037FFFH-030000H 02FFFFH-028000H 027FFFH-020000H 01FFFFH-018000H 017FFFH-010000H 00FFFFH-008000H 007FFFH-007000H 006FFFH-006000H 005FFFH-005000H 004FFFH-004000H 003FFFH-003000H 002FFFH-002000H 001FFF-001000H 000FFFH-000000H PRELIMINARY (May, 2002, Version 0.0) 11 AMIC Technology, Inc. A29DL324 Series Table 5. A29DL324 Top Boot Sector Group Address Table Sector Group SGA0 SGA1 A20 0 0 A19 0 0 A18 0 0 A17 0 0 A16 0 0 1 1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 X X X X X X X X X X X X X X 0 0 1 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 Remark X: VIH or VIL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) FSA63 FSA64 FSA65 FSA66 FSA67 FSA68 FSA69 FSA70 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 192 KB (3 Sectors) FSA4-FSA7 FSA8-FSA11 FSA12-FSA15 FSA16-FSA19 FSA20-FSA23 FSA24-FSA27 FSA28-FSA31 FSA32-FSA35 FSA36-FSA39 FSA40-FSA43 FSA44-FSA47 FSA48-FSA51 FSA52-FSA55 FSA56-FSA59 FSA60-FSA62 A14 X X A13 X X A12 X X Size 64 KB (1 Sector) 192 KB (3 Sectors) Sector FSA0 FSA1-FSA3 PRELIMINARY (May, 2002, Version 0.0) 12 AMIC Technology, Inc. A29DL324 Series Table 6. A29DL324 Bottom Boot Sector Group Address Table Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 A20 0 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 0 A17 0 0 0 0 0 0 0 0 0 A16 0 0 0 0 0 0 0 0 0 1 1 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X 0 0 1 SGA24 Remark X: VIH or VIL 1 1 1 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 X X X 64 KB (1 Sector) FSA70 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 256 KB (4 Sectors) 192 KB (3 Sector) FSA11-FSA14 FSA15-FSA18 FSA19-FSA22 FSA23-FSA26 FSA27-FSA30 FSA31-FSA34 FSA35-FSA38 FSA39-FSA42 FSA43-FSA46 FSA47-FSA50 FSA51-FSA54 FSA55-FSA58 FSA59-FSA62 FSA63-FSA66 FSA67-FSA69 A14 0 0 0 0 1 1 1 1 X A13 0 0 1 1 0 0 1 1 X A12 0 1 0 1 0 1 0 1 X Size 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 8 KB (1 Sector) 192 KB (3 Sectors) Sector FSA0 FSA1 FSA2 FSA3 FSA4 FSA5 FSA6 FSA7 FSA8-FSA10 PRELIMINARY (May, 2002, Version 0.0) 13 AMIC Technology, Inc. A29DL324 Series Table 7. A29DL324 Product ID Code (Manufacture Code / Device Code) Product ID Code A12 to A20 Manufacturer Code Device BYTE Top Code mode Boot Bottom Boot WOR Top Boot D mode Bottom Boot Sector Group Protection X VIL VIL VIH X X X VIL VIL VIL VIL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 10H 50H 53H 2250H 2253H 01H Note2 VIL VIL VIL VIL Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 Sector VIL VIH VIL VIL Group Address 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Input Note 1 Output HEX A6 A1 A0 A-1 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Notes: 1. A-1 is valid only in the BYTE mode. I/O8 to I/O14 go into a high-impedance state in the BYTE mode, and I/O15 is A-1 of the lowest address. 2. If 01H is output, the sector group is protected. If 00H is output, the sector group is unprotected. Remark X: VIH or VIL PRELIMINARY (May, 2002, Version 0.0) 14 AMIC Technology, Inc. A29L323 Series Sector Group Protection This command performs sector group protection. By applying VID to RESET and writing 60H to any address, the device enters the sector group protection mode. Sector group protection is started by inputting the sector group address of the sector group to be protected to A12 to A20, inputting (A6, A1, A0) = (VIL, VIH, VIL), and writing 60H. After a timeout of 250s, sector group protection is completed. Next, with the sector group address input to A12 to A20, the device enters the sector group protection verify mode by inputting (A6, A1, A0) = (VIL, VIH, VIL), and writing 40H. When read is performed in this state, the sector group protection verify result is output to I/O0. If "1" is output to I/O0, the verified sector group is protected. If "1" was not output to I/O0, sector group protection failed, so perform sector group protection again. For the timing waveform and flow chart, refer to Timing Waveform for Sector Group Protection and Figure 1. Query The dual operation flash memory conforms to CFI (Common Flash memory Interface). CFI enables information about a device such as the device specifications, memory density, and supply voltage to be read. Therefore, the software of the host system can support the software algorithm of a specific vendor used by a device by using the CFI. For details, refer to the CFI specifications. By writing the Query command (98H) and giving an address, the device information corresponding to that address can be read. If the device information is read in the WORD mode (16 bits), the upper bytes of data (I/O15 to I/O8) are "0". To end the Query mode, writes the read / reset command. Extra One Time Protect Sector Entry The dual operation flash memory has a sector area that has One Time Protect function. This area does not allow code that has been written to the area to be changed. This area can be programmed or erased until it is protected. Once it has been protected, however, protection can never be canceled. Therefore, care must be exercised when using this area. The Extra One Time Protect Sector area has a density of 64 Kbytes and exits at the same addresses as the 8 Kbytes sector. These addresses are 3F0000H to 3FFFFFH for top boot in the BYTE mode (1F8000H to 1FFFFFH in the WORD mode), and 000000H to 00FFFFH for bottom boot in the BYTE mode (000000H to 007FFFH in the WORD mode). Because boot block areas (8 Kbytes x 8 sectors) usually appear in the areas of these addresses, the Extra One Time Protect Sector entry command sequence must be written to enter them as the Extra One Time Protect Sector area. The status in which the Extra One Time Protect Sector area appears is the Extra One Time Protect Sector mode. In the Extra One Time Protect Sector mode, the other sectors, except the boot block area, can be read. In addition, the Extra One Time Protect Sector area can be read, programmed, or erased in this mode. To exit from the Extra One Time Protect Sector mode, the Extra One Time Protect Sector Reset command sequence must be written. Sector Group Unprotect This command performs sector group unprotect. Sector group unprotect is performed for all sector group. Unprotect cannot be performed for specific sector group. Moreover, all sector groups must be protected priors to unprotect. The device enters the sector group unprotect mode by applying VID to RESET and writing 60H to any address. If unprotected sector group exist, first perform sector group protection for these sector groups. To protect a sector group, input the sector group address of the sector group to be protected to the sector group address input pin, input (A6, A1, A0) = (VIL, VIH, VIL), and write 60H (refer to Sector Group Protection). Sector group unprotect is started by inputting (A6, A1, A0) = (VIH, VIH, VIL), and writing 60H to any address. Following a timeout of 15 ms, sector group unprotect is completed. Unprotect verification must be performed for each sector group. The device enters the sector group unprotect verification mode by inputting the sector group address to input pin of sector group address and writing 40H, with input (A6, A1, A0) = (VIH, VIH, VIL). If reading is performed in this state, the sector group unprotect verification result is output to I/O0. If the verified sector group is unprotected, "0" is output to I/O0. If "0" is not output to I/O0, this means that unprotect failed, so perform sector group unprotect again. For the flow chart, refer to Figure 2. Sector Group Unprotect Flow Chart. Extra One Time Protect Sector Program To program data to the Extra One Time Protect Sector area, write the Extra One Time Protect Sector Program command sequence in the Extra One Time Protect Sector mode. This command is no different from the conventional program command except that it must be written in the Extra One Time Protect Sector mode. Therefore, completion of execution of this command is detected in the same manner as the conventional detection method of using I/O7 data polling, I/O6 toggle bit, and RY/ BY . Care must be exercised in selecting a program destination address. If a program destination address other than the one in the Extra One Time Protect Sector area is selected, the data of that address is changed. PRELIMINARY (May, 2002, Version 0.0) 15 AMIC Technology, Inc. A29DL324 Series Extra One Time Protect Sector Erase To erase the Extra One Time Protect Sector area, write the Extra One Time Protect Sector erase command sequence in the Extra One Time Protect Sector mode. This command is the same as the conventional sector erase command except that it must be written in the Extra One Time Protect Sector mode. Therefore, completion of execution of this command is detected in the same manner as the conventional detection method of using I/O7 data polling, I/O6 toggle bit, and RY/ BY . Care must be exercised in selecting a sector address to erase. If a sector address other than the one in the Extra One Time Protect Sector area is selected, the data of that sector is changed. This device requires two unlock cycles for program / erase command sequence to prevent illegal program / erase. Moreover, a hardware data protect function is provided as follows. Low VCC Write Inhibit To prevent an illegal write cycle during VCC transition, the command register and program / erase circuit is disabled and all write cycles are ignored while VCC is VLKO or lower. Write commands are ignored until VCC becomes equal to or greater than VLKO. Logical Inhibit The write cycle is inhibited under any of the following conditions : OE = VIL, CE = VIH, or WE = VIH. To start a write cycle, CE = VIL and WE = VIL must be set while /OE = VIH. Extra One Time Protect Sector Protection The following write operations are used to protect the Extra One Time Protect area during the Extra One Time Protect Sector mode. Write the sector group protection setup command (60H) in the Extra One Time Protect Sector mode. . Set (A6, A1, A0) = (VIL, VIH, VIL), and set the sector address that selects the Extra One Time Protect Sector. . Write the sector group protection command (60H). Because the sequence is the same as the conventional command sequence to protect a sector group except that the Extra One Time Protect Sector mode must be set and that VID is not input to the RESET , the same command sequence can be used. For details of how to protect a sector group, refer to Sector Group Protection. If an address other than the one of the Extra One Time Protect Sector area is specified as a sector address, the other sectors are affected. Once the sector has been protected, protection can never be canceled. Exercise utmost care when protecting a sector. Power-Up Write Inhibit Even if WE = CE = VIL and OE = VIH are satisfied at power-up, no commands are accepted at the rising edge of WE . The device is automatically reset to the read mode at power ON. Write Pulse "Glitch" Protection Because OE , CE , and /WE reject a noise pulse of 5 ns (typical) or less as an invalid pulse, a write operation is not started. Sector Group Protection The dual operation flash memory can be protected by the user in sector group units. For details, refer to Sector Group Protection. Hardware Data Protection PRELIMINARY (May, 2002, Version 0.0) 16 AMIC Technology, Inc. A29L323 Series START RESET=V ID Wait 4 us Temporary Sector Group Unprotect Mode No Protect Sector Group? Yes Sector Group Protection (Unprotect) Mode Address=Don't care Data=60H Pulse Count=1 Sector Group Protection (A6, A1, A0)=(V IL, VIH, VIL), Address=SGA, Data=60H Increment Pulse Count Timeout 250us Verify Sector Group Protection (A6, A1, A0)=(V IL, VIH, VIL), Address=SGA, Data=40H Read from Sector Group Address (A6, A1, A0)=(V IL, VIH, VIL), Address=SGA No No Data=01H? Data=01H? Yes Remove VID from RESET, Write Reset Command Yes Protect Other Sector Group? No Yes Next Sector Group Address Fail Remove V ID from RESET, Write Reset Command Sector Group Protect Complete Figure 1. Sector Group Protection Flow Chart PRELIMINARY (May, 2002, Version 0.0) 17 AMIC Technology, Inc. A29L323 Series START RESET=VID Wait 4 us Sector Group Protection Address=Don't Care, Data=60H Yes All Sector Group Protected? No n=0 Verify Sector Group Protection (A6, A1, A0)=(VIL, VIH, VIL) A12 to A20=SGA, Data=40H Read from Sector Group Address (A6, A1, A0)=(VIL, VIH, VIL), A12 to A20=SGA Sector Group Protection No Data=0H? Yes Last Sector Group (n=25)? Yes n=0, Pluse Count=1 Sector Group Unprotect (A6, A1, A0)=(VIH, VIH, VIL), Data=60H Timeout 15ms No Next Sector Group Address (n=n+1) Increment Pulse Verify Sector Group Protection (A6, A1, A0)=(VIH, VIH, VIL), Address=SGA, Data=40H Read from Sector Group Address (A6, A1, A0)=(VIH, VIH, VIL), A12 to A20=SGA No Pulse Count=1000? Yes No Data=00H? Yes Yes Last Sector Group (n=25)? Yes Remove VID from RESET, Write Reset Command Remove VID from RESET, Write Reset Command Next Sector Group Address (n=n+1) Fail Sector Group Protect Complete Figure 2. Sector Group Unprotect Flow Chart PRELIMINARY (May, 2002, Version 0.0) 18 AMIC Technology, Inc. A29L323 Series CFI Code List Address A6 to A0 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH Data I/O15 to I/O0 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0027H Description "QRY" (ASCII code) Main command set 2 : AMD/FJ standard type Start address of PRIMARY table Auxiliary command set 00H : Not supported Start address of auxiliary algorithm table Minimum VCC voltage (program / erase) I/O7 to I/O4 : 1 V/bit I/O3 to I/O0 : 100 mV/bit Maximum VCC voltage (program / erase) I/O7 to I/O4 : 1 V/bit I/O3 to I/O0 : 100 mV/bit Minimum VPP voltage Maximum VPP voltage N Typical word program time (2 s) N Typical buffer program time (2 s) N Typical sector erase time (2 ms) N Typical chip erase time (2 ms) N Maximum word program time (typical time x 2 ) N Maximum buffer program time (typical time x 2 ) N Maximum sector erasing time (typical time x 2 ) N Maximum chip erasing time (typical time x 2 ) N Capacity (2 Bytes) I/O information 2 : x8/x16-bit organization N Maximum number of bytes when two banks are programmed (2 ) Type of erase block Information about erase block 1 Bit0 to 15 : y = number of sectors Bit16 to 31 : z = size (Z x 256 Bytes) Information about erase block 2 bit0 to 15 : y = number of sectors bit16 to 31 : z = size (z x 256 Bytes) "PRI" (ASCII code) 1CH 0036H 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 40H 41H 42H 0000H 0000H 0004H 0000H 000AH 0000H 0005H 0000H 0004H 0000H 0016H 0002H 0000H 0000H 0000H 0002H 0007H 0000H 0020H 0000H 003EH 0000H 0000H 0001H 0050H 0052H 0049H PRELIMINARY (May, 2002, Version 0.0) 19 AMIC Technology, Inc. A29DL324 Series CFI Code List (continued) Address A6 to A0 43H 44H 45H Data I/O15 to I/O0 0031H 0032H 0000H Description Main version (ASCII code) Minor version (ASCII code) Address during command input 00H : Necessary 01H : Unnecessary Temporary erase suspend function 00H : Not supported 01H : Read only 02H : Read / Program Sector group protection 00H : Not supported 01H : Supported Temporary sector group protection 00H : Not supported 01H : Supported Sector group protection algorithm Number of sectors of bank 2 00H : Not supported 20H : A29DL324 Burst mode 00H : Not supported Page mode 00H : Not supported Minimum VACC voltage I/O7 to I/O4 : 1 V/bit I/O3 to I/O0 : 100 mV/bit Maximum VACC voltage I/O7 to I/O4 : 1 V/bit I/O3 to I/O0 : 100 mV/bit Boot organization 02H : Bottom boot (A29DL324UX-XX) 03H : Top boot (A29DL324TX-XX) Temporary program suspend function 00H : Not supported 01H : Supported 46H 0002H 47H 0001H 48H 0001H 49H 4AH 0004H 00XXH 4BH 4CH 4DH 0000H 0000H 0085H 4EH 0095H 4FH 00XXH 50H 0001H PRELIMINARY (May, 2002, Version 0.0) 20 AMIC Technology, Inc. A29DL324 Series Command Definitions Writing Commands All operations are executed by writing a command. To write a command, the write cycle of a standard microprocessor is used. The operation of the device is controlled by writing a command to a register. The command register is a function that latches the address and data necessary for executing an instruction and does not occupy the memory area. If an illegal address or data is written or if an address or data is written in the wrong sequence, the device is reset to the read mode. Table 8. shows the commands and command sequences. Following write by command sequence, the pulse required for program is automatically generated inside the device and program verification is automatically performed, so that control from external is not required. During automatic program, any command other than the program suspend is ignored. However, automatic program is interrupted when hardware reset is performed. Since the programmed data is not guaranteed in this case, reexecute the program command following completion of reset. Upon completion of automatic program, the device returns to the read mode. The operation status of automatic program can be determined by using the hardware sequence flags (I/O7, I/O6, RY/ BY pins). See sections "I/O7 (Data Polling)", "I/O6 (Toggle Bit)", and "RY/ BY (Ready / Busy )". For the timing waveform and flow chart, refer to Timing Waveform for Write Cycle ( WE Controlled), Timing Waveform for Write Cycle ( CE Controlled) and Figure 3. Read / Reset Command This command resets the device to the read mode. The read mode is maintained until the contents of the command register are changed. Once the device is in the read mode, no command is necessary for reading data. Data read can be performed using the read cycle of a standard microprocessor. The read mode is maintained until the contents of the command register are changed. START Product ID The manufacturer code and device code can be read without inputting a high voltage to the address pin. If a bank address is specified in the third bus cycle and a read operation is started from address xx00H in the fourth bus cycle, manufacturer code 10H is output. If address xx02H (BYTE mode) or xx01H (WORD mode) is read, the device code is output. If a read operation is executed from an address in the bank not specified in the third bus cycle, data of the memory cell is output. If a read operation is executed starting from address (BA) 02H (WORD mode) or (BA) 04H (BYTE mode), information indicating which sector group is protected can be obtained. If the sector group address is scanned with (A6, A1, A0) = (VIL, VIH, VIL), "1" is output to I/O0 to indicate that the sector group is protected (for details refer to Sector Group Protection). The product ID can be read only from the specified bank. To read the manufacturer code, device code, and information on protection of sector group from a bank not specified, write the read / reset command, specify the bank address to be read, and then write the product ID command again. To end the product ID mode, writes the read / reset command. To write the product ID command in the product ID mode, execute the read / reset command once. Write Program Command Sequence Data Poll from System Yes No Increment Address Last Address ? Yes Programming Completed Program Command Sequence This command is used to program data. Program is performed in 1 byte or 1 word units. Program can be performed regardless of the address sequence, even if the sector limit is exceeded. However, "0" cannot be changed back into "1" through the program operation. If overwriting "1" to "0" is attempted, the program operation is interrupted and "1" is output to I/O5, or successful program is indicated in data polling, but actually the data is "0" as before. Figure 3. Program Flow Chart PRELIMINARY (May, 2002, Version 0.0) 21 AMIC Technology, Inc. A29DL324 Series Program Suspend / Resume Commands This command is used to suspend automatic programming. Addresses not being programmed to while programming is suspended can be read. Sector erase (including the timeout period) and data program operations can be both suspended. Chip erase operations cannot be suspended. 1s is required between when the command sequence is programmed and when the automatic program operation is suspended. The execution status of an automatic program operation can be determined using a hardware sequence flag (I/O7, I/O6 pins.) refer to I/O7 (Data polling) and I/O6 (Toggle Bit). To resume an automatic program operation, write the resume command (30H) while the operation is suspended. Caution about Program Suspend / Resume Commands If automatic program resume and suspend are repeated at intervals of less than 5s, the program operation may not be correctly completed. timeout period. In this case, the timeout period starts again after the last erase command has been written. If a protected sector and a sector that is not protected are included in the selected sectors, only the sector that is not protected is erased and the protected sector is ignored. If a command other than the sector erase or erase suspend command is input during the timeout period, the device is reset to the read mode. If the timeout period has elapsed and erase has started, any command other than the erase suspend command is ignored. However, erase is stopped if hardware reset is executed. In this case, sector erase is not guaranteed. Execute the sector erase command again after completion of reset. When automatic erasure has been completed, the device returns to the read mode. Completion of automatic sector erase can be reported to the host system by using the data polling function of I/O7, toggle bit function of I/O6, and RY/ BY pin. Sector erase is started after the lapse of the timeout period that is started from the rising of the WE or CE pulse, whichever earlier, of the last sector erase command and is completed when the data of I/O7 is set to "1" (refer to Hardware Sequence Flags). The device returns to the read mode. Data polling and toggle bit function in any address of the sector that is to be erased. The time required to erase two or more sectors is "(sector programming time + sector erase time) x number of sectors". If two or more sectors of different banks are erased, a read operation from a bank (i.e., dual operation) cannot be executed. For the timing waveform and flow chart, refer to Timing Waveform for Sector / Chip Erase and Figure 4. Chip Erase Command Sequence This command is used to erase the entire chip. Following command sequence write, erase is performed after "0" is written to all memory cells and verification is performed, using the automatic erase function. Program before erase and control from external are not required. During automatic erase, all commands that have been written are ignored. However, automatic erase is interrupted by hardware reset. Since erase is not guaranteed in this case, execute the chip erase command again after reset is completed. Upon completion of automatic erase, the device returns to read mode. The automatic erase operation status can be determined with the hardware sequence flags (I/O7, I/O6, RY/ BY pins). See sections "I/O7 (Data Polling)", "I/O6 (Toggle Bit)", and "RY/ BY (Ready / Busy )". For the timing waveform and flow chart, refer to Timing Waveform for Sector / Chip Erase and Figure 4. Sector Erase Command Sequence This command is used to erase data in sector units. "0" is written to the entire sector whose data is to be erased by the automatic erase function after the command sequence has been written, and erase is executed after verification has been performed. Programming before erase and external control are not necessary. The timeout period of sector erase starts when erase command 30H and the address of the sector to be erased are written at the sixth bus cycle. When this timeout period (50s) has elapsed, the device automatically starts erasing. Two or more sectors can be selected and erased at the same time by additionally writing erase command 30H and the address of the sector whose data is to be erased during the START Write Erase Command Sequence Data Poll from System Data = FFh ? No Yes Erasure Completed Figure 4. Sector / Chip Erase Flow Chart PRELIMINARY (May, 2002, Version 0.0) 22 AMIC Technology, Inc. A29DL324 Series Sector Erase Suspend / Resume Commands This command suspends automatic erase. During erase suspend, sectors for which erase is not performed can be read and programmed. Sector erase (including the timeout period) and data program operations can be both be suspended. Chip erase operations cannot be suspended. Suspend can be performed for all sectors for which erase is being performed. Following command sequence write, 20s are required until automatic erase is suspended. While automatic erase is suspended, any sector for which erase is not being performed can be read and programmed. Whether automatic erase is suspended can be determined with the hardware sequence flags (I/O7, I/O6, I/O2 pins). See sections "I/O7 (Data Polling)", "I/O6 (Toggle Bit)", and "I/O2 (Toggle Bit II)". If resume automatic erase that has been suspended, write the resume command (30H) while sector erase is suspended. At this time, input a bank address of the sector for which erasure is suspended. Caution Sector Erase Suspend / Resume Commands If automatic erase resume and suspend are repeated at intervals of less than 100s, the erasure operation may not be correctly completed. START Address=555H Data=AAH Address=2AAH Data=55H Unlock Bypass Set Address=555H Data=20H Address=Don't Care Data=A0H Address=Program Address Data=Program Data Data Polling Unlock Bypass Program No Next Address Last Address ? Unlock Bypass Command Sequence This device provides an unlock bypass mode to shorten the program time. Normally, 4 write cycle included with 2 unlock cycles are required during program. In contrast, with the unlock bypass mode, it is possible to perform program without unlock cycles. In the unlock bypass mode, all commands except unlock bypass program and unlock bypass reset are ignored. To end the unlock bypass mode, the unlock bypass reset command must be written. Note, however, that the unlock bypass reset command must be written to an address of the bank that is not being read in dual operation. If the unlock bypass reset command is written, the device returns to the normal read mode. In the unlock bypass mode, the operating current is necessary even if CE = VIH. For the flowchart, refer to Figure 5. Unlock Bypass Set Figure 5. Unlock Bypass Flow Chart (WORD Mode) Yes Programming Completed Address=BA Data=90H Unlock Bypass Reset Address=Don't Care Data=00H End Note: This flow chart shows the WORD mode's case. In the BYTE mode, address to be input is different from the WORD mode. See Table 8. Command Sequence This command sets the device to the unlock bypass mode. Unlock Bypass Program This command is used to perform program in the unlock bypass mode. Unlock Bypass Reset This command is used to quit the unlock bypass mode. When this command is executed, the device returns to the read mode. PRELIMINARY (May, 2002, Version 0.0) 23 AMIC Technology, Inc. A29L323 Series Table 8. A29DL324 Command Sequence Command Sequence Bus 1 Bus Cycle 2nd Bus Cycle Cycle Address Data Address Data 1 XXXH F0H RA RD 3 AAAH AAH 555H 55H 4 1 1 6 6 1 1 3 2 2 3 555H AAAH 555H BA BA AAAH 555H AAAH 555H BA BA AAAH 555H XXXH BA AAAH 555H 4 4 1 3 XXXH XXXH AAH 55H AAAH 555H AAAH 555H AAAH 555H AAAH 555H XXXH 60H 60H 98H AAH AAH B0H 30H AAH AAH B0H 30H AAH A0H 90H AAH 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH PA XXXH 555H 2AAH SPA SUA 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 60H 60H 55H 55H 55H 55H 55H PD 00HNote11 55H st 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Read / Reset Note 1 Read / Reset Note 1 BYTE mode Program WORD mode BYTE mode WORD mode Address Data Address Data Address Data Address Data AAAH F0H RA RD 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H (BA) AAAH (BA) 555H SPA SUA AAAH 555H AAAH 555H AAAH 555H AAAH 555H 40H 40H 88H SPA SUA SD SD A0H 80H 80H 20H 90H PA AAAH 555H AAAH 555H IA PD AAH AAH ID 555H 2AAH 555H 2AAH 55H 55H AAAH 555H FSA 10H 30H - Program Suspend Note2 Program Suspend Note3 Chip Erase BYTE mode WORD mode BYTE mode WORD mode Sector Erase Suspend Note4 Sector Erase Suspend Resume Sector Erase Note5 Unlock Bypass Set BYTE mode WORD mode Unlock Bypass Program Note6 Unlock Bypass Reset Note7 Product ID BYTE mode WORD mode Sector Group Protection Note7 Sector Group Unprotect Note8 Query Note9 BYTE mode WORD mode Extra One Time BYTE mode Protect Sector WORD mode Entry Extra One Time BYTE mode Protect Sector WORD mode Program Note10 Extra One Time BYTE mode Protect Sector WORD mode Erase Note10 Extra One Time BYTE mode Protect Sector WORD mode Reset Note10 Extra One Time Protect Sector Protection Note10 4 AAH 55H A0H PA PD - - - - 6 AAH 55H 80H AAAH 555H XXXH AAH 555H 2AAH - 55H EOTPSA 30H 4 AAH 55H 90H 00H - - - 4 60H EOTPSA 60H EOTPSA 40H EOTPSA SD - - - - Note: 1. Both these read / reset commands reset the device to the read mode. 2. Programming is suspended if B0H is input to the bank address being programmed to in a program operation. 3. Programming is resumed if 30H is input to the bank address being suspended to in a program-suspend operation. 4. Erasure is suspended if B0H is input to the bank address being erased in a sector erase operation. 5. Erasure is resumed if 30H is input to the bank address being suspended in a sector-erase-suspend operation. 6. Valid only in the unlock bypass mode. 7. Valid only when RESET = VID (except in the Extra One Time Protect Sector mode). 8. The command sequence that protects a sector group is excluded. PRELIMINARY (May, 2002, Version 0.0) 24 AMIC Technology, Inc. A29DL324 Series 9. Only A0 to A6 are valid as an address. 10. Valid only in the Extra One Time Protect Sector mode. 11. This command can be used even if this data is F0H. Remarks: 1. Specify address 555H or 2AAH (A10 to A0) in the WORD mode, and AAAH or 555H (A10 to A0, A-1) in the BYTE mode. 2. RA : Read address RD : Read data IA : Address input xx00H (to read the manufacturer code) xx02H (to read the device code in the BYTE mode) xx01H (to read the device code in the WORD mode) ID : Code output. Refer to the Product ID code (Manufacturer code / Device code). PA : Program address PD : Program data FSA: Erase sector address. The sector to be erased is selected by the combination of this address. Refer to the Sector Organization / Sector Address Table. BA : Bank address. Refer to the Sector Organization / Sector Address Table. SPA : Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (VIL, VIH, VIL). SUA : Unprotect sector group address. Set sector group address (SGA) and (A6, A1, A0) = (VIH, VIH, VIL). EOTPSA : Extra One Time Protect Sector area addresses. These addresses are 3F0000H to 3FFFFFH (BYTE mode) / 1F8000H to 1FFFFFH (WORD mode) for top boot, and 000000H to 00FFFFH (BYTE mode) / 000000H to 007FFFH (WORD mode) for bottom boot. SD : Data for verifying whether sector groups read from the address specified by SPA, SUA, and EOTPSA are protected or unprotected. 3. The sector group address is don't care except when a program / erase address or read address are selected. 4. x of address bit indicates VIH or VIL. PRELIMINARY (May, 2002, Version 0.0) 25 AMIC Technology, Inc. A29DL324 Series Hardware Sequence Flags The status of automatic program / erase operations can be determined from the status of the I/O2, I/O3, I/O5, I/O6, I/O7, and RY /BY pins. read after automatic program / erase is complete or when it is suspended, the I/O6 toggle operation is stopped, and valid data for the read is output. If a sector for which erasure is suspended is read, "1" will be output to I/O6. Continuous read control is performed with the OE or CE . If program is performed for an address inside a protected sector, I/O6 is toggled approximately 1s, and then the device is reset to the read mode. Moreover, if all the sectors selected at the time of automatic erase are protected, I/O6 is toggled approximately 400s, and then the device is reset to the read mode. In this way, by using I/O6, it is possible to determine the status of automatic erase is in progress (or suspended), but to determine which sector is being erased, I/O2 (Toggle Bit II) is used. See section "I/O2 (Toggle Bit II)". For the timing waveform and flow chart, refer to Timing Waveform for Toggle Bit, Timing Waveform for I/O2 vs. I/O6 and Figure 7. Caution When Reading Flags When checking the completion or suspension status of an automatic program / erase operation by reading different sector data within the same bank, be sure to either clock the CE or change the address before reading the data. If the CE is fixed to VIL or data is read from the same address without the address being changed, the output data may not be output correctly. I/O7 : Data Polling Data polling is a function to determine the status of automatic program / erase is currently being performed by using I/O7. Data polling is valid from the rise of the last WE in the program / erase command sequence. The status of automatic program is currently being executed can be determined by reading from the program destination addresses. While automatic programming is being executed or while automatic programming is being executed during erasure suspension, the complement of the final data programmed will be output to I/O7. Upon completion of automatic program, the true value of the programmed data, not the complement, is output. The status of automatic erase is in progress can be determined by reading from the addresses of the sector being erased. If erase is in progress, "0" is output to I/O7. If the automatic erase operation is complete or if it is suspend, "1" will be output to I/O7 when a sector for which erasure is suspended is read. During automatic erase, if all the selected sectors are protected, data polling is valid for approximately 400s. The device is then reset to the read mode. If the selected sectors include protected and unprotected sectors, only unprotected sectors are erased, and protected sectors are ignored. Upon completion of automatic program / erase, after the data output to I/O7 changes from the complement to the true value, I/O7 changes asynchronously like I/O0 to I/O6 while OE is maintained at low level. For the timing waveform and flow chart, refer to Timing Waveform for Data Polling and Figure 6. START Read (I/O 0 to I/O 7) An=Valid Address I/O7=Data? No I/O5=1? Yes No Read (I/O 0 to I/O 7) An=Valid Address Yes I/O7=Data? No FAIL Yes PASS I/O6 : Toggle Bit The toggle bit is a function that uses I/O6 to determine the status of automatic program / erase is in progress. The toggle bit is valid from the rise of the last WE in the program / erase command sequence. If a continuous read is performed from any address of a bank that is undergoing automatic program or erase, I/O6 will be toggled. If a sector other than the erased sector is Figure 6. Data Polling Flow Chart PRELIMINARY (May, 2002, Version 0.0) 26 AMIC Technology, Inc. A29L323 Series I/O2: Toggle Bit II Toggle bit II is a function that determines the status of automatic erase (or erase suspend) is in progress for a particular sector by using I/O2. I/O2 is toggled when continuous read is performed from addresses in a sector during automatic erase (or erase suspend). Either OE or CE is used to control continuous read. When program to a sector that is not subject to erase suspend is attempted during erase suspend, read from sectors that are not subject to erase suspend cannot be performed until program is completed. In this case, "1" will be output to I/O2 if a continuous read is performed from an address in a sector other than an erased sector. In this way, it is possible to determine the status of automatic erase (including erase suspend) is in progress for sectors specified using I/O2, but whether the state is erase in progress or erase suspend cannot be determined with I/O2. To determine this, I/O6 (Toggle Bit) must be used. See section "I/O6 (Toggle Bit)". For the timing waveform, refer to Timing Waveform for I/O2 vs. I/O6. RYBY : Read/ Busy The RY/ BY is a dedicated output pin used to check the status of automatic program / erase is in progress. During automatic program / erase, "0" is output to the RY /BY . If "1" is output, this signifies that the device is either in the read mode (including erase suspend) or standby mode. Since the RY/ BY is an open-drain output pin, it is possible to connect several RY/ BY in series by connecting a pull-up resistor to VCC. For the timing waveform, refer to Timing Waveform for RY/BY (Ready / Busy ). START Read (I/O0 to I/O7) An=Any Address in the Bank Being Executed I/O5 : Exceeding Timing Limits If the program / erase time exceeds the prescribed number of pulses during automatic program / erase (exceeding timing limit), "1" is output to I/O5 and automatic program / erase failure is indicated. Moreover, if overwriting "0" to "1" is attempted, the device judges data overwrite to be impossible, and "1" is output to I/O5 when the timing limit is exceeded. When this happens, execute command reset. I/O7=Toggle? Yes I/O5=1? Yes No No Read (I/O0 to I/O7) An=Any Address in the Bank Being Executed I/O3 : Sector Erase Timer A 50s timeout period occurs following write with the sector erase command sequence before automatic erase starts. During this timeout period, "0" is output to I/O3. When automatic erase starts upon completion of the timeout period, "1" is output to I/O3. If sector erase is performed, first confirm whether the device has received a command by using I/O7 (Data Polling) or I/O6 (Toggle Bit). Then, using I/O3, check whether automatic erase has started. If I/O3 is "0", the timeout period is not over, and so it is possible to add sectors to erase. If I/O3 is "1", automatic erase starts and other commands (except erase suspend) are ignored until erase is completed. If a sector to erase is added during the sector erase timeout period, it is recommended to check I/O3 prior to and following the addition. If I/O3 is "1" following the addition, that addition may not be accepted. I/O7=Toggle? No FAIL No PASS Figure 7. Toggle Bit Flow Chart PRELIMINARY (May, 2002, Version 0.0) 27 AMIC Technology, Inc. A29DL324 Series Table 9. Hardware Sequence Flags Status Progress Program Erase Program Suspend I/O7 (Note 1) I/O6 (Note 2) Toggle Toggle Data Data 1 Data Toggle Toggle Toggle Toggle I/O5 (Note 3) 0 0 Data Data 0 Data 0 1 1 1 0 1 Data Data 0 Data 0 0 1 0 I/O3 I/O2 (Note 1) 1 Toggle Data Data Toggle Data 1 1 N/A N/A 0 0 Data 1 1 1 0 0 0 0 RY/BY I/O7 0 Program Sector Other than Program Sector Erase Suspend Sector Other than Erase Suspend Sector Erase Suspend Program Data Data 1 Data Erase Suspend I/O7 0 0 Exceeding time limits Program Erase Erase Suspend Erase Suspend Program I/O7 Notes: 1. To read I/O7 or I/O2, a valid address must be input. 2. To read I/O6, any address can be used. 3. For I/O5, "1" is output if the automatic program / erase time exceeds the prescribed number of internal pulses. PRELIMINARY (May, 2002, Version 0.0) 28 AMIC Technology, Inc. A29DL324 Series Electrical Characteristics Before turning on power, input GND 0.2 V to the RESET pin until VCC VCC (MIN.). DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current Output leakage current Power Read BYTE mode Supply Current WORD mode Program, Erase Standby Symbol VIH VIL VOH VOL ILI ILO ICC1 VCC = VCC (max.), CE = VIL, OE = VIH tCYCLE = 5 MHz tCYCLE = 1 MHz tCYCLE = 5 MHz tCYCLE = 1 MHz ICC2 ICC3 VCC = VCC (max.), CE = VIL, OE = VIH VCC = VCC (max.), CE = RESET = IOH = -500 A, VCC = VCC (min.) IOL = +1.0 mA, VCC = VCC (min.) -1.0 -1.0 10 2 10 2 15 0.2 Test Description Min. 2.4 -0.3 2.4 Typ. Max. VCC+0.3 +0.5 0.4 +1.0 +1.0 16 4 16 4 30 5 mA A Unit V V V V A A mA WP (ACC) = VCC 0.3 V, OE = VIL Standby / Reset Automatic sleep mode Read during programming Read during erasing Programming during suspend Accelerated programming ICC4 ICC5 ICC6 ICC7 ICC8 IACC VID VACC VLKO VCC = VCC (max.), RESET = GND 0.2 V VIH = VCC 0.2 V, VIL = GND 0.2 V VIH = VCC 0.2 V, VIL = GND 0.2 V VIH = VCC 0.2 V, VIL = GND 0.2 V 0.2 0.2 21 21 17 5 15 11.5 8.5 5 5 45 45 35 10 30 12.5 9.5 1.7 V V V A A mA mA mA mA CE = VIL, OE = VIH, Automatic programming during suspend WP (ACC) pin VCC High Voltage is applied High Voltage is applied VIH = VCC 0.3V; VIL = VSS 0.3V RESET high level input voltage Accelerated programming voltage Low VCC lock-out voltage (Note) Notes: 1. When VCC is equal to or lower than VLKO, the device ignores all write cycles. Remark: These DC characteristics are in common regardless of product classification. PRELIMINARY (May, 2002, Version 0.0) 29 AMIC Technology, Inc. A29L323 Series AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time 3.0V 1.5V 0V Output Waveform Test points 1.5V 5 ns) 1.5V Test points 1.5V Output Load 1 TTL + 30pF Read Cycle Parameter Read cycle time Address access time Symbol tRC tACC tCE tOE tDF tOH tRP tRH tREADY tELFL/tELFH tFLQZ tFHQV 85 Test Condition Min. 85 Typ. Max. 85 85 40 30 0 500 50 20 5 30 Unit Notes ns ns ns ns ns ns ns ns s ns ns ns CE = OE = VIL OE = VIL CE = VIL OE = VIL or CE = VIL CE access time OE access time Output disable time Output hold time RESET pulse width RESET hold time before read RESET low to read mode CE low to /BYTE low, high BYTE low output disable time BYTE high access time Remark: tDF is the time from inactivation of CE or OE to Hi-Z state output. PRELIMINARY (May, 2002, Version 0.0) 30 AMIC Technology, Inc. A29DL324 Series AC Characteristics Write Cycle (Program / Erase) Parameter Write cycle time Address setup time ( WE to address) Address setup time ( CE to address) Address hold time ( WE to address) Address hold time ( CE to address) Input data setup time Input data hold time Read Toggle bit, Data polling Read recovery time before write ( OE to CE ) Read recovery time before write ( OE to WE ) tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tBPG tWPG tSER tVCS tRB tRP tRRB tRH tEOE tBUSY tASO tAHT 15 0 50 0 500 20 50 85 90 Symbol tWC tAC tAS tAH tAH tDS tDH tOEH Min. 85 0 0 45 45 35 0 0 10 0 0 0 0 0 0 35 35 30 30 9 11 0.7 200 200 5 ns ns ns ns ns ns ns ns ns ns s s s s ns ns s ns ns ns ns ns 1 Typ. Max. Unit ns ns ns ns ns ns ns ns Notes OE hold time WE setup time ( CE to WE ) CE setup time ( WE to CE ) WE hold time ( CE to WE ) CE hold time ( WE to CE ) Write pulse width CE pulse width Write pulse width high CE pulse width high Byte programming operation time Word programming operation time Sector erase operation time VCC set time RY/BY recovery time RESET pulse width RESET high-voltage (VID) hold time from high of RY/ BY when sector group is temporarily unprotect RESET hold time From completion of automatic program / erase to data output time RY/BY delay time from valid program or erase operation Address setup time to OE low in toggle bit Address hold time to CE or OE high in toggle bit PRELIMINARY (May, 2002, Version 0.0) 31 AMIC Technology, Inc. A29DL324 Series Write Cycle (Program / Erase) (continued) Parameter Symbol tCEPH tOEPH tVLHT tVIDR tVACCR tTOW tSPD Min. 20 20 4 500 500 50 20 Typ. Max. Unit ns ns s ns ns s s 2 3 2 4 4 Notes CE pulse width high for toggle bit OE pulse width high for toggle bit Voltage transition time Rise time to VID (RESET) Rise time to VACC ( WE (ACC)) Erase timeout time Erase suspend transition time Notes: 1. The preprogramming time prior to the erase operation is not included. 2. Sector group protection and accelerated mode only. 3. Sector group protection only. 4. Table only. Write operation (Erase / Program) Performance Parameter Sector erase time Chip erase time Byte programming time Word programming time Chip programming time Accelerated programming time Erase / Program cycle Description Excludes programming time prior to erasure Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead 1,000,000 BYTE mode WORD mode Min. Typ. 0.7 50 9 11 40 25 7 150 s cycle 200 200 Max. 5 Unit s s s s s PRELIMINARY (May, 2002, Version 0.0) 32 AMIC Technology, Inc. A29DL324 Series Timing Waveform for Read Cycle (1) tRC Addresses (Input) tACC CE (Input) tCE OE (Input) tOEH WE (Input) I/O (Output) High-Z Data Out High-Z tOE tOH tDF Addresses Stable Timing Waveform for Read Cycle (2) tRC Addresses (Input) tRP CE (Input) tREADY tCE OE (Input) tOH High-Z High-Z tRH tACC Addresses Stable I/O (Output) Data Out PRELIMINARY (May, 2002, Version 0.0) 33 AMIC Technology, Inc. A29DL324 Series Timing Waveform for Sector Group Protection VCC VID tVCS VIH tVIDR RESET (Input) tVLHT tWC tWC Address (Input) SGAx SGAx SGAy A0 (Input) A1 (Input) A6 (Input) CE (Input) OE (Input) WE (Input) tWP TIMEOUT tOE I/O (Input / Outpu) 60H 60H 40H 01H (Note) 60H Note: The sector group protection verification result is output 01H: The sector group is protected. 00H: The sector group is not protected PRELIMINARY (May, 2002, Version 0.0) 34 AMIC Technology, Inc. A29DL324 Series Timing Waveform for Temporary Sector Group Unprotect VCC VID tVCS tVLHT VIH tVIDR RESET (Input) WE (Input) Program or Erase Command Sequence tRRB ~ ~ CE (Input) ~~ ~~ tVLHT RY/BY (Output) tVLHT Period during which protection is canceled Timing Waveform for Accelerated Mode VCC VID tVCS tVLHT ~ ~ VIH RESET (Input) CE (Input) tVACCR Program or Erase Command Sequence tRRB ~ ~ WE (Input) ~~ ~~ tVLHT RY/BY (Output) tVLHT Accelerated mode period PRELIMINARY (May, 2002, Version 0.0) 35 AMIC Technology, Inc. A29DL324 Series Timing Waveform for Dual Operation tRC tWC tRC tWC tRC tWC Address (Input) BA1 tAS BA2 tAH tACC BA1 BA2 BA1 tAHT tAS BA2 CE (Input) tCE tCEPH OE (Input) tGHWL tWP tOEH tOE tDF WE (Input) tDS tDH tDF I/O (Input / Outpu) Output Input Output Input Output Status Timing Waveform for Write Cycle ( WE Controlled) 3rd and 4th write cycle Addresses (Input) 555H tWC tAS PA tAH Data Polling PA tRC CE (Input) tGHWL OE (Input) tWP tBPG or tWPG WE (Input) tCH tCE tCS tWPH tDH tOE I/O (Input / Output) A0H tDS PD I/O7 DOUT DOUT tOH Note : 1. This timing waveform shows the last two write cycles among the program command sequence's four write cycles, and data polling. 2. This timing waveform shows the WORD mode's case. In the BYTE mode, address to be input is different from the WORD mode. See Table 8. Command Sequence. 3. PA : Program address PD : Program data I/O7 : The output of the complement of the data written to the device. DOUT : The output of the data written to the device. PRELIMINARY (May, 2002, Version 0.0) 36 AMIC Technology, Inc. A29DL324 Series Timing Waveform for Write Cycle ( CE Controlled) 3rd and 4th write cycle Addresses (Input) 555H tWC tCP CE (Input) tGHWL OE (Input) tWH tWS WE (Input) tBPG or tWPG tAS PA tAH Data Polling PA tRC tCPH tCE tDS tDH tOE I/O (Input / Output) A0H PD I/O7 DOUT DOUT tOH Note : 1. This timing waveform shows the last two write cycles among the program command sequence's four write cycles, and data polling. 2. This timing waveform shows the WORD mode's case. In the BYTE mode, address to be input is different from the WORD mode. See Table 8. Command Sequence. 3. PA : Program address PD : Program data I/O7 : The output of the complement of the data written to the device. DOUT : The output of the data written to the device. PRELIMINARY (May, 2002, Version 0.0) 37 AMIC Technology, Inc. A29DL324 Series Timing Waveform for Sector / Chip Erase tRC tWC Address (Input) 555H 2AAH tAH 555H 555H 2AAH FSA (Note) CE (Input) tCS tCH OE (Input) tGHWL tWP tWPH WE (Input) tDS tDH (10H for chip erase) 55H 80H AAH 55H 30H I/O (Input / Outpu) tVCS AAH VCC Note : 1. FSA is the sector address to be erased. In the case of chip erase, input 555H (WORD mode), AAAH (BYTE mode). 2. This timing chart shows the WORD mode's case. In the BYTE mode, address to be input is different from the WORD mode. See Table 8. Command Sequence. PRELIMINARY (May, 2002, Version 0.0) 38 AMIC Technology, Inc. A29DL324 Series Timing Waveform for Data Polling CE (Input) tCH OE (Input) tOEH tCE WE (Input) tBPG, tWPG, tSER I/O7 (Output) I/O7 DOUT (Note) tOE tDF Hi-Z I/O0-I/O6 (Output) Status Data Valid Data Hi-Z tBUSY RY/BY(Output) tEOE Note : 1. I/O7 = DOUT : True value of program data (indicates completion of automatic program / erase) PRELIMINARY (May, 2002, Version 0.0) 39 AMIC Technology, Inc. A29DL324 Series Timing Waveform for Toggle Bit Addresses (Input) VA tAHT tAHT tAS CE (Input) tASO tCEPH WE (Input) tOEPH tOEH tOEH OE (Input) tDH tOE tCE I/O6, I/O2 (Input / Output) Input Data Toggle Toggle Toggle Stop Toggle (note) Valid Data Out tBUSY RYBY (Output) Note : 1. I/O6 stops the toggle (indicates automatic program / erase completion). Timing Waveforms for I/O2 vs. I/O6 ~ ~ ~ ~ ~ ~ ~ ~ WE (Input) Erasure Erase Suspend Read I/O6 (Output) Erase Suspend Read Erase Suspend Input of Program Command Erasure ~ ~ Completion of Erasure Input of Automatic Erase Command Erase Suspended Erase Suspended Input of Program Command Erase Resumed ~ ~ ~ ~ ~ ~ I/O2 (Output) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Toggle I/O2 and I/O 6 (CE or OE is used for toggle) PRELIMINARY (May, 2002, Version 0.0) 40 AMIC Technology, Inc. ~ ~ ~ ~ A29DL324 Series Timing Waveform for RY/BY (Read / Busy) CE (Input) Rising Edge of the Last Write Pulse WE (Input) ~ ~ Automatic Program or Erase RY/BY (Output) tBUSY Timing Waveform for RESET / RY / BY WE (Input) RESET (Input) tRB RY/BY (Output) tRP tRPD Timing Waveform for BYTE Failing Edge of Last Write Pulse OE, WE (Input) Input Determined BYTE (Input) tAH tAS PRELIMINARY (May, 2002, Version 0.0) 41 AMIC Technology, Inc. A29DL324 Series Timing Waveform for BYTE Mode Switching CE (Input) BYTE (Input) tELFL I/O0 to I/O 14 (Output) Hi-Z Data Output I/O0 to I/O 14 tACC I/O15 (Output), A-1(Input) Hi-Z Data Output I/O15 tFLQZ Address Input A-1 Data Output I/O0 to I/O 7 Hi-Z Timing Waveform for WORD Mode Switching CE (Input) tCE BYTE (Input) tELFH I/O0 to I/O 14 (Output) Hi-Z Data Output I/O0 to I/O 7 Data Output I/O0 to I/O 14 Hi-Z I/O15 (Output), A-1(Input) Address Input A-1 tFHQV Data Output I/O15 Hi-Z PRELIMINARY (May, 2002, Version 0.0) 42 AMIC Technology, Inc. A29DL324 Series Latch-up Characteristics Description Input Voltage with respect to VSS on all I/O pins VCC Current Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET) Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time. Min. -1.0V -100 mA -1.0V Max. VCC+1.0V +100 mA 12.5V Capacitance (TA = 25C, f = 1MHz) Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Setup VIN=0 VOUT=0 Typ. 6 8.5 Max. 7.5 12 Unit pF pF Notes: 1. VIN : Input voltage, VOUT : Output voltage 2. These parameters are not 100% tested. Data Retention Parameter Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years PRELIMINARY (May, 2002, Version 0.0) 43 AMIC Technology, Inc. A29DL324 Series Ordering Information Access Time (ns) Operating Supply Voltage (V) Part No. Boot Sector Top Address (Sector) (T type) Bottom Address (Sector) Package A29DL324TV-90 A29DL324UV-90 90 A29DL324TG-90 A29DL324UG-90 2.7 to 3.6 48Pin TSOP 48Pin TSOP 63-ball TFBGA 63-ball TFBGA (B type) Top Address (Sector) (T type) Bottom Address (Sector) (B type) PRELIMINARY (May, 2002, Version 0.0) 44 AMIC Technology, Inc. A29DL324 Series Package Information TSOP 48L (Type I) Outline Dimensions unit: inches/mm D D1 1 48 A2 A E 25 c 0.25 L Dimensions in inches Min 0.002 0.037 0.007 0.004 0.779 0.720 0.016 0 Nom 0.039 0.009 0.787 0.724 0.472 0.020 BASIC 0.020 0.011 Typ. 0.004 8 0 0.024 0.40 Max 0.047 0.006 0.042 0.011 0.008 0.795 0.728 0.476 Dimensions in mm Min 0.05 0.94 0.18 0.12 19.80 18.30 Nom 1.00 0.22 20.00 18.40 12.00 0.50 BASIC 0.50 0.28 Typ. 0.10 8 0.60 Max 1.20 0.15 1.06 0.27 0.20 20.20 18.50 12.10 24 Detail "A" Detail "A" Symbol A A1 A2 b c D D1 E e L S y Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. PRELIMINARY (May, 2002, Version 0.0) 45 AMIC Technology, Inc. S e b y D A1 A29DL324 Series Package Information 63 BALLS TFBGA (7 x 11mm) Outline Dimensions unit: mm TOP VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 M A B C 0.05 M C Ball*A1 CORNER 0.35 87 654321 A B C D E F G H J K L M 4 5.6 0.7 11.00 0.05 8.8 7.00 0.05 A 1.1 0.8 B SIDE VIEW 0.25 0.05 1.2 MAX. SEATING PLANE C 0.08 C // 0.1 C PRELIMINARY (May, 2002, Version 0.0) 46 AMIC Technology, Inc. |
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